The present invention relates generally to a semiconductor device and, more particularly, to a multiplexing circuit.
Generally, a multiplexing circuit selects one of a plurality of signals and outputs the selected signal, or successively and separately outputs the plurality of signals to a single output terminal at set time intervals. As described above, the multiplexing circuit is mainly used as a circuit for selectively outputting specific input signals.
FIG. 1 is a diagram schematically illustrating a conventional multiplexing circuit. Referring to FIG. 1, the multiplexing circuit 10 includes a selection circuit 11, an output circuit 12 and an initialization circuit 13. The operation of the multiplexing circuit 10 is briefly described below with reference to FIG. 2. First, the initialization circuit 13 initializes the voltage level of the output node OUT of the selection circuit 11 to a predetermined voltage in response to a power-up signal PWRUP. Thereafter, when selection control signals SEL1˜SELN (N is integer) are sequentially enabled, input signals SCLK1˜SCLKN (N is integer) are sequentially and separately output to the output node OUT as the selection output signal SO. The output circuit 12 outputs a multiplexing output signal OUTEN in response to the selection output signal SO received via the output node OUT.
Meanwhile, the load of the selection circuit 11 increases as the number of the input signals, which are input to the selection circuit 11, increases. The reason for this is that when the number of input signals of the selection circuit 11 increases, the selection circuit 11 must further include circuits for selecting the additional input signals. When the load of the selection circuit 11 increases, a point at which the selection circuit 11 outputs the selection output signal SO to the output node OUT is delayed. For example, when the input signals SCLK1˜SCLK3 and SCLK6˜SCLKN are logic low, and the input signals SCLK4 and SCLK5 are logic high, it is preferred that the selection output signal SO become logic high when the selection control signal SEL4 is enabled, and, thereafter, become logic high when the selection control signal SEL5 is disabled.
However, due to the load of the selection circuit 11, as illustrated in FIG. 2, the selection output signal SO is delayed for time T from a point, at which the selection control signal SEL4 is enabled, and then becomes logic high. As a result, the point at which the multiplexing circuit 10 outputs the multiplexing output signal OUTEN is delayed. As described above, when the output time point for the multiplexing circuit 10 is delayed, a circuit (not shown) for performing a specific operation in response to the output signal of the multiplexing circuit 10 may operate erroneously.